 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| dm9081 10base-t hub controller final 1 version: dm9081-ds-f01 april 22, 1997 general description the 10base-t hub controller (dm9081) provides a system level s olution for designing ieee-compliant 802.3 repeaters that incorporate 10base-t transceivers. this device integrates the repeater functions specified by section 9 of the ieee 802.3 standard. the twisted pair transceiver is compliant with 10base-t standards. the dm9081 provi des eight integral twisted pair media attachment units (maus) and two attachment unit interface (aui) ports in a 100-pin qfp package. the total number of ports per repeater unit can be increased by connecting multiple dm9081 chips via their expansion ports. the dm9081 supports led drivers to monitor port status. it displays link, carrier sense, collision, partition, and bit rate error status. in minimum mode, link, carrier sense, and collision status can be displayed without external ttl devices. block diagram tx mux preamble jam signal fifo manchester decoder rx mux aui port1 aui port2 tp port0 tp port7 pll manchester encoder * * * * * data in data out mux state machine timer led port2 led port1 expansion port nrz data expin# expout# dat rxp1 rxn1 cdp1 cdn1 txp1 txn1 rxp2 rxn2 cdp2 cdn2 txp2 txn2 rxd0+ rxd0- tpo0+ dtpo0+ dtpo0- tpo0- rxd7+ rxd7- tpo7+ dtpo7+ dtpo7- tpo7- aui1_crs_led aui2_crs_led col_led aui_led tp_bit_led tp_pol_led tp_jab_led traffic_led tp_par_led tp_link_led tck led_latch rx_clk
dm9081 2 final version: dm9081-ds-f01 april 22, 1997 table of contents general description....................................................... 1 block diagram .............................................................. 1 table of contents.......................................................... 2 features......................................................................... 3 pin configuration .......................................................... 3 pin description.............................................................. 4 functional description .................................................. 6 repeater function ....................................................... 6 signal regeneration ................................................... 6 collision function...................................................... 6 auto partition/reconnection ...................................... 6 fragment extension ................................................... 6 link integrity test ..................................................... 6 jabber lockup protection ........................................... 7 reset .......................................................................... 7 expansion port........................................................... 7 external logic ........................................................... 8 led functions........................................................... 9 collision status.......................................................... 9 aui1 port status ........................................................ 9 aui2 port status ........................................................ 9 minimum mode ......................................................... 9 tp port status ............................................................ 9 normal mode........................................................... 10 led latch ............................................................... 10 aui ports status ...................................................... 11 tp ports bit rate error status .................................. 11 tp ports jabber status.............................................. 11 tp ports partition status ...........................................11 traffic status............................................................11 tp port link status ..................................................11 dm9081 chip external components ........................12 absolute maximum ratings.........................................13 dc electrical characteristics .......................................13 ac characte ristics .......................................................14 timing waveforms expansion port input timing ...................................15 expansion port output timing .................................15 expansion port collision timing..............................16 aui transmit timing...............................................16 aui receive t iming.................................................17 aui collision timing...............................................17 transmit timing ......................................................17 receive t iming ........................................................18 link integrity timing...............................................18 layout recommendation decoupling ...............................................................19 power plane..............................................................19 package information ....................................................21 ordering information...................................................22 company overview......................................................22 contact windows.........................................................22 dm9081 final 3 version: dm9081-ds-f01 april 22, 1997 features repeater functions comply with ieee 802.3 repeater unit specification eight integral 10base-t transceivers utilize the required pre-distortion transmission technique two attachment unit interface (aui) ports allow connection with 10base5 (ethernet) and 10base2 (cheapernet) networks design a dumb hub in minimum mode by using minimum external logic that can respond to link, carrier sense and collision status from led supports one led output per port for additional status indicators such as link, partition, carrier sense, etc. built-in jabber led reports global jabber information of the dm9081 hub built-in traffic led indicates hub global 10mhz bandwidth utilization status expandable to accommodate two dm9081 connections, with no external logic required on board pll, manchester encoder/decoder and fifo expandable to accommodate increased number of repeater ports. recommended ic cascade number: under 3 and inclusive preamble loss effects eliminated by deep fifo each port can be isolated (partitioned) and reconnected separately twisted pair link test capability full amplitude and timing regeneration for retransmitted signals low power cmos process with single 5v supply 100-pin qfp package pin configuration dtpo3- tpo3- dv dd dv dd li/rx7 li/rx6 li/rx5 li/rx4 dv dd li/rx3 li/rx1 li/rx0 li/rx2 aui1_crs_led x1 col_led reset# testpin1 testpin0 dgnd expin# dat expout# tck nc x2 nc dv dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 30 27 29 80 79 78 77 76 75 74 72 73 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 cdp2 cdn2 rxp2 rxn2 txp2 txn2 cdp1 cdn1 rxp1 agnd rxd0- rxd1+ rxd2- rxd3+ rxd3- rxd4+ rxd4- rxd5+ rxd5- rxd6+ rxd6- rxd7+ rxd7- 50 49 48 47 46 45 44 43 42 40 41 39 38 37 36 35 34 33 32 31 dv dd tpo7+ dtpo7+ dtpo7- tpo7+ dgnd tpo6+ dtpo6- dtpo6+ tpo6- dv dd tpo5+ dtpo5+ dtpo5+ tpo5- dgnd tpo4+ dtpo4+ dtpo4- tpo4- 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 tpo3+ dtpo3+ dtpo1+ dtpo1- tpo1- av dd agnd DM9081F dgnd dv dd tpo0+ dtpo0- tpo0- dgnd tpo1+ dv dd tpo2+ dtpo2+ dtpo2- tpo2- dgnd aui1_crs_led rxd2+ rxd1- rxd0+ av dd txn1 txp1 rxn1 dtpo0+ led_latch aui_led tp_bit_led tp_pol_led tp_jab_led traffic_led tp_par_led tp_link_led dm9081 4 final version: dm9081-ds-f01 april 22, 1997 pin description pin no. pin name i/o description transceiver 100, 1 99, 2 34, 31 33, 32 39, 36 38, 37 44, 41 43, 42 49, 46 48, 47 84, 87 85, 86 89, 92 90, 91 94, 97 95, 96 dtpo3+/- tpo3+/- tpo4+/- dtpo4+/- tpo5+/- dtpo5+/- tpo6+/- dtpo6+/- tpo7+/- dtpo7+/- tpo0+/- dtpo0+/- tpo1+/- dtpo1+/- tpo2+/- dtpo2+/- o tp driver outputs . the tpo+/- output generate 10mbits/s manchester- encoded data. the dtpo+/- outputs are one-half bit time delayed and inverted with respect to tpo+/-. these four o utputs provide the tp drivers with pre-distortion capability 52, 51 54, 53 56, 55 58, 57 60, 59 62, 61 64, 63 66, 65 rxd7+/- rxd6+/- rxd5+/- rxd4+/- rxd3+/- rxd2+/- rxd1+/- rxd0+/- i 10base-t port different data receivers 70, 69 76, 75 txp1, txn1 txp2, txn2 o aui port different data drivers . the outputs are source followers that require a 270 ? pull-down resistor 72, 71 78, 77 rxp1, rxn1 rxp2, rxn2 i aui port differential receive input pair 74, 73 80, 79 cdp1, cdn1 cdp2, cdn2 i aui port different collision input pair expansion port 24 expout# o the assertion of this signal indicates that dm9081 is trans mitting data on dat pins. it is active low 22 expin# i the assertion of this signal indicates that dm9081 is r eceiving data on dat pins. the receiving data w ill be broadcast to the other ports. it is active low and is internally pulled high with a 100k ? resistor 23 dat i/o,z the dat pins of all dm9081 chips are inter-connected. the active dm9081 drives dat with repeated data or jam signals in nrz format. the inactive dm9081 r eceives the repeated data or jam signals from the dat pin dm9081 final 5 version: dm9081-ds-f01 april 22, 1997 pin description pin no. pin name i/o description miscellaneous 3, 4, 9, 30, 40, 50, 83, 93 dv dd p digital power 14, 21, 35, 45, 88, 98 dgnd p digital ground 18 reset# i active low to reset the internal logic of dm9081. it should be synchronized to x2 if multiple dm9081s are used 20, 19 testpin0 testpin1 i these two pins are used to select led display mode. normal mode is selected if both pins are connected to v dd . minimum mode is selected if both pins are connected to gnd. other se ttings are prohibited 26, 29 nc - these pins should be left open 27 x2 i a 20mhz oscillator or crystal should be attached to this pin 28 x1 o this pin is used in crystal connection only. it is left open when using an oscillator 67, 81 av dd p analog power 68, 82 agnd p analog ground led display pins 5led_latch (li/rx7) o this pin is used to latch the serial led information from pins 6 to 13 in minimum mode, this pin sends out tp7 link and carrier sense status 6aui_led (li/rx6) o this pin transmits aui port status s ynch ronous to tck in minimum mode, this pin sends out tp6 link and carrier sense status 7tp_bit_led (li/rx5) o this pin sends out global bit rate error status of the dm9081 hub in minimum mode, this pin sends out tp5 link and carrier sense status 8 tp_pol_led (li/rx4) o in minimum mode, this pin sends out tp4 link and carrier sense status 10 tp_jab_led (li/rx3) o this pin transmits global jabber status of the dm9081 hub in minimum mode, this pin sends out tp3 link and carrier sense status 11 traffic_led (li/rx2) o this pin sends out utilization of 10mhz bandwidth synchronous to tck in minimum mode, this pin sends out tp2 link and carrier sense status 12 tp_par_led (li/rx1) o this pin sends out the partition status synchronous to tck for the eight tp ports in minimum mode, this pin sends out tp1 link and carrier sense status 13 tp_link_led (li/rx0) o this pin sends out the link and carrier sense status synchronous to tck for the eight tp ports in minimum mode, this pin sends out tp0 link and carrier sense status 15 aui1_crs_led o active low for 52ms when aui port 1 detects carrier 16 aui2_crs_led o active low for 52ms when aui port 2 detects carrier 17 col_led o active low for 26ms when collision is detected 25 tck o a 10mhz clock synchronous to x2 dm9081 6 final version: dm9081-ds-f01 april 22, 1997 functional description the dm9081 integrated multiport controller is a single chip implementation of an ieee 802.3 ethernet repeater (hub). the dm9081 chip provi des eight integral 10base-t ports plus two aui ports, comprising the basic repeater. the dm9081 is also expandable, enabling the implementation of high port count repeaters based on more than one dm9081 chip. the dm9081 chip complies with the full set of repeater basic functions, as defined in section 9 of iso 8802.3 (ansi/ieee 802.3c). these functions are summarized below. repeater function when any single network port senses the start of a packet on its receive lines, the dm 9081 chip will broadcast the received d ata to all other network ports. the repeated data will also be presented on the expansion port to provide multiple dm9081 chip repeater applications. signal regeneration when re-transmitting a packet, the dm9081 chip makes sure that the outgoing packet complies with the 802.3 specification in terms of preamble instructions, voltage amplitude and timing characteristics. data packets repeated by the dm9081 chip will contain a minimum of 62 preamble bits before the start of frame delimiter. finally, signal symmetry is restored to data packets repeated by the dm9081 chip, removing jitter and distortion caused by network cabling. collision function the dm9081 will detect and respond to collision conditions as specified in ieee 802.3. a multiple dm9081 repeater (hub) implementation also complies with the 802.3 specification. specifically, a repeater based on one or more dm9081 chips will handle the transmit collision and one-port-left collision conditions correctly. auto partition/reconnection the dm9081 monitors any tp ports or aui ports and partitions them once certain criteria are met. tp ports and aui ports will be partitioned un der exte nded duration or when frequent collisions occur. each tp port and the aui port are partitioned separately, and are independent of other network ports. the dm9081 chip will cause the port to partition under either of following conditions. 1. a collision condition exists continuously for 1024-bit times (for example, when the aui port sqe signal is active and the tp port is transmitting simultaneously and receiving). 2. whenever each of 32 consecutive attempts to transmit to that port results in a collision. any partitioned port can be reco nnected if a packet longer than 512-bit times is transmitted or r eceived from that port without collision. fragment extension if the total packet length received by the dm9081 is less than 96 bits, including preamble, the dm 9081 chip will extend the repeated packet length to 96 bits by a ppending a jam sequence to the original fragment. link integrity test the integral tp ports implement the link test function, as specified in the 802.3 10base-t standard. the dm9081 will transmit link test pu lses to any tp port after that port transmitter has b een inactive for more than 8ms but less than 17 ms. conversely, if a tp port does not receive any data packets or link test pulses for more than 65ms but less than 132ms, that port w ill enter link fail state. a port in link fail state w ill be disabled by the dm9081 chip (repeater transmit functions are disabled) until it recei ves either four consecutive link test pulses or a data packet. note, however, that the dm9081 chip will always transmit link test pulses to all tp ports regardless of whether the port is enabled, par titioned, or in link fail state. dm9081 final 7 version: dm9081-ds-f01 april 22, 1997 jabber lockup protection the dm9081 chip implements a built-in jabber protection scheme to ensure that the network is not disabled due to transmission of excessively long data p ackets. this protection scheme will automatically interrupt the transmitter circuits of the dm9081 for 96-bit times if the dm9081 chip has been transmitting continuously for more than 65,536-bit times. this is referred to as mau jabber lockup protection (mjlp). reset an internal circuit ensures that a minimum reset pulse is generated for all internal circuits. for a reset input with a slow rising edge, the input buffer threshold may be crossed several times due to ripples on the input waveform. during reset, the output signals are placed in their inactive states. this means that all analog signals are placed in their idle states, bidirectional signals are not driven, active low signals are driven high, and all active high signals and the led_latch pin are driven low. in a multiple dm9081 chip repeater, the reset signal should be applied simultaneously to all dm9081 chips, and should be synchrononized to the external x2 clock. table 1 summarizes the state of the dm9081 chip following reset. function state after reset pull up/pull down dat hi-impedance no transmitters (tp and aui) idle nc receivers (tp and aui) enabled terminate aui partition/reconnection reconnect n/a tp port partition/reconnection reconnect n/a link test function for tp ports enabled n/a active low output high no active high output low no table 1. initial s tate of dm9081 expansion port the dm9081 chip expansion port is comprised of three pins: a bi-directional signal (dat), an input signal (expin#), and an output signal (expout#). these signals are used for multiple-dm9081 chip repeater applications. in this configuration, all dm9081 chips must be synchronized with a common clock connected to the x2 inputs. an external synchronnous reset is required. the dm9081 expansion scheme allows the use of multiple dm9081 chips in either a single repeater or a modular multiple repeater with backplane architecture. the dat pins of all dm9081 chips must be interconnected. the dat pin is a bidirectional i/o pin that can be used to transfer data or a jam signal between the dm9081 chips. the data sent over the dat line is in nrz format, and is synchronized to the common clock. in the multiple dm9081 configuration, the dm9081 chip asserts the expout# pin to indicate that it is active and is ready to drive the dat pin. an external logic senses the expout# line from all the dm9081 chips and asse rts the expin# line to each dm9081. the active dm9081 asserts expout#, and sends data or jam on the dat line. other inactive dm9081 detect expin# asserted, and receive data on the dat line. if more than one dm9081 chip asserts expout# lines, then all dm9081s will broastcast jam signals. dm9081 8 final version: dm9081-ds-f01 april 22, 1997 external logic a simple logic scheme is required when more than two dm9081 chips are connected to increase the total number of repeater ports. the external logic should h ave one input (expout#) and one output (expin#) for each dm9081 chip. this function is easily implemented in a pal device, using the following logical equations: expin1# = expout2# & expout3# & ?.. expoutn# expin2# = expout1# & expout3# & ?.. expoutn# expin3# = expout1# & expout2# & ?.. expoutn# . . . . . . . . . . . . expinn# = expout1# & expout2# & ?.. expoutn-1# the above equations are in pos itive logic, i.e., a variable is true when asserted. an example of three banked dm9081 chips is shown in figure 1. the cascade ic number recommended: under 3 and inclusive. note that if the design includes only two dm 9081 chips, then expout1# is connected to expin2#, expout2# is connected to expin1#, and no external logic is required. a single pal16l8 performs the arbitration function for a repeater based on several dm9081 chips. figure 1. multiple d m9081 devices dm9081 final 9 version: dm9081-ds-f01 april 22, 1997 led functions the dm9081 provides led functions to monitor the tp and aui ports. collision status the col_led pin displays the collision status of the dm9081. when the dm9081 detects a collision, the col_led will drive low for more than 26ms and less than 52ms. aui1 port status the aui1_crs_led displays the aui1 port status of the dm9081. when the dm9081 r eceives a data packet from aui1 port, the aui1_crs_led pin will drive low for 52ms, then drive high at least 78ms until it responds to the next packet. aui2 port status the aui2_crs_led displays the aui2 port status of the dm9081. when the dm9081 r eceives a data packet from the aui2 port, the aui2_crs_led pin will drive low for 52ms, then drive high at least 78ms until it responds to the next packet. minimum mode in minimum mode, testpin0 and testpin2 should be pulled low and li/rxn (n = 0 ~ 7) pins drive the led without using external ttl logic. the description is given below in "tp ports status." tp ports status the li/rxn (n=0 ~ 7) pin sends out the status for tp ports 0-7 of the dm9081. in link test fail state, the li/rxn pin is driven high. in link test pass, the li/rxn pin is driven low. when tp port receives a packet, the li/rxn pin is driven high for 78ms, then driven low at least 52ms until it responds to the next packet. an example is shown in figure 2. figure 2. minimum mode implementation dm9081 10 final version: dm9081-ds-f01 april 22, 1997 normal mode in normal mode, testpin0 and testpin1 must be pulled high. the col_led, aui1_crs_led and aui2_crs_led pins are defined as minimum mode, whereas the other led drive pins require external devices to display the status from the led pins. these pins transmit information from the dm 9081 by first s ending bit 7. a detailed timing diagram is given in figure 3. the shift logic and latch device shown in figure 4 is used to convert received serial data into byte- oriented data. the output data is used to drive the led. led latch the led_latch pin is used to latch the byte-oriented data. the rising edge of the tck clock, occurring on the high state led_latch, is used to strobe in the state of the following led pins. b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b1 b6 b5 b4 b3 b2 b7 tck li_rxn led_latch figure 3. serial led signal timing figure 4. normal mode implementation dm9081 final 11 version: dm9081-ds-f01 april 22, 1997 aui ports status the aui_led pin transmits the status of dm9081's two aui ports on the falling edge of tck. figure 5 shows a typical external hardware setup employed to convert a serial bit stream into parallel form. the accuracy of the aui signals is within 8 bit times (bt). the contents of the output data for the aui_led are as followed: bit 0: aui port 1 partition status (0: if par tition) bit 1: aui port 1 bit rate error status (0: if bit rate error) bit 2: aui port 1 jabber status (0: if jabber) bit 3: aui port 1 loopback status (0: if loopback error) bit 4: aui port 2 partition status (0: if par tition) bit 5: aui port 2 bit rate error status (0: if bit rate error) bit 6: aui port 2 jabber status (0: if jabber) bit 7: aui port 2 loopback status (0: if loopback error) tp ports bit rate error status the tp_bit_led pin sends out global bit rate error information of the dm9081's hub. tp ports jabber status the tp_jab_led pin sends out global jabber information of the dm9081's hub. tp ports partition status the tp_par_led pin transmits partition information for the dm9081's eight tp ports on the falling edge of tck. figure 4 shows a typical external hardware configuration employed to convert the serial bit stream into parallel form. the accuracy of the partition signals is 8 bit. if a tp port is in partition status, its corresponding bit is set to low. the contents of the output data for the tp_par_led are as followed: bit 0: tp port 0 partition status bit 1: tp port 1 partition status bit 2: tp port 2 partition status bit 3: tp port 3 partition status bit 4: tp port 4 partition status bit 5: tp port 5 partition status bit 6: tp port 6 partition status bit 7: tp port 7 partition status traffic status the traffic_led pin transmits a utilization report for the 10mhz bandwidth on the falling edge of tck. figure 4 shows a typical external hardware configuration employed to convert the serial bit stream into parallel form. the accuracy of the traffic signals is 8 bit. the corresponding bit is set to low, if the following conditions are met. the contents of the output data for the traffic_led are as followed: bit 0: over 1% utilization of 10mhz bandwidth bit 1: over 6.25% utilization of 10mhz bandwidth bit 2: over 12.5% utilization of 10mhz bandwidth bit 3: over 25% utilization of 10mhz bandwidth bit 4: over 37.5% utilization of 10mhz bandwidth bit 5: over 50% utilization of 10mhz bandwidth bit 6: over 62.5% utilization of 10mhz bandwidth bit 7: over 87.5% utilization of 10mhz bandwidth as shown above, if all 8 bits are active low, the utilization is in excess of 87.5% for the 10mhz bandwidth. tp ports link status the tp_link_led transmits link information for the dm9081's eight tp ports on the falling edge of tck. figure 5 shows a typical external hardware configuration employed to convert the serial bit stream into parallel form. the accuracy of the link signals is within 8 bit. if a tp port is line fail, its corresponding bit is set to high. if a tp port is line pass, its corresponding bit is set to low. when this port receives a packet, its corresponding bit is set high for 78ms, then driven low at least 52ms until it responds to the next packet. the contents of the output data for the tp_link_led are as followed: bit 0: tp port 0 link/receive status bit 1: tp port 1 link/receive status bit 2: tp port 2 link/receive status bit 3: tp port 3 link/receive status bit 4: tp port 4 link/receive status bit 5: tp port 5 link/receive status bit 6: tp port 6 link/receive status bit 7: tp port 7 link/receive status dm9081 12 final version: dm9081-ds-f01 april 22, 1997 dm9081 chip external com ponents figure 5 shows a typical twisted pair port external components schematic diagram. the resistor used should have a 1% tolerance to ensure compliance with 10base-t networks. the filters and pulse transformers are n ecessary devices that have a major impact on the performance and compliance of the 10base-t repeater ports. specifically, the transmitted waveforms are heavily influenced by the filter characteristics, and the twisted pair r eceivers employ several criteria to continuously monitor the incoming signals' amplitude and timing characteristics to determine the necessity and the time to assert the internal carrier sense. for these reasons, it is crucial that the values of the resistors and the tolerances of the external components comply with given specifications. several manufacturers produce modules that combine the functions of the transmit filters, r eceive f ilters, and pulse transformers into one package. figure 5. typical single tp port using external components figure 6. typical single aui port using components dm9081 final 13 version: dm9081-ds-f01 april 22, 1997 absolute maximum ratings* *comments supply voltage (v dd ) ..............................-0.5v to +7.0v dc input voltage (v in )....................-0.5v to v cc +0.5v dc output voltage (v out ) ..............-0.5v to v cc +0.5v storage temperature range (tstg) ........-65 c to +150 c power dissipation (pd) ...........................................1.2w lead temp. (tl) (soldering, 10sec.) ..................... 260 c esd rating (rzap=1.5k, czap=100pf) ................ 2000v stresses above those listed under "abs olute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (v dd =5v 5%, t a =0 c to 70 c, unless otherwise specified.) symbol parameter min. typ. max. unit conditions v il input low voltage -0.5 0.8 v dgnd=0.0v, except dat v ih input high voltage 2.0 dv dd +0.5 v except dat v ol output low voltage - 0.4 v i ol =4ma v oh output high voltage 2.4 - v i oh =-4ma i il input leakage current (also dat as input) - 10 ua dgnd dm9081 final 15 version: dm9081-ds-f01 april 22, 1997 timing waveforms expansion port input timing symbol parameter min. typ. max. unit conditions t djset dat setup time - 20 ns t djhold dat hold time 60 - ns x2 tck expout expin dat t djset in t djhold expansion port output timing symbol parameter min. typ. max. unit conditions t hrl tck rising edge to expout# driven low - 20 ns cl=100pf t hrh tck rising edge to expout# driven high - 20 ns cl=100pf t hdr tck rising edge to dat driven - 20 ns cl=100pf t hdz tck rising edge to dat not driven - 20 ns cl=100pf x2 tck expout expin dat t hrl t hdr t hrh t hdz out dm9081 16 final version: dm9081-ds-f01 april 22, 1997 expansion port collision timing symbol parameter min. typ. max. unit conditions t doff dat data off - 20 ns cl=100pf x2 tck expin dat out t doff expout aui transmit timing symbol parameter min. typ. max. unit conditions t txtd x2 rising edge to txp/txn toggle - 30 ns t txtr txp, txn rise time (10% to 90%) 2.5 5.0 ns t txtf txp, txn fall time (90% to 10%) 2.5 5.0 ns t txrm txp, txn rise & fall time mismatch - 1.0 ns x2 txp txn t txtd t txtr t txtf 1111 0010 dm9081 final 17 version: dm9081-ds-f01 april 22, 1997 aui receive timing symbol parameter min. typ. max. unit conditions t pworx rxp/rxn pulse width accept/reject threshold 15 45 ns |v in |>|v asq | t pwkrx rxp/rxn pulse width maintain/turn-off threshold 136 200 ns |v in |>|v asq | rxp/rxn vasq tpwkrx t pworx t pwkrx aui collision timing symbol parameter min. typ. max. unit conditions t pwocd cdp/cdn pulse width accept/reject threshold 10 26 ns |v in |>|v asq | t pwkcd cdp/cdn pulse width maintain/turn-off threshold 90 160 ns |v in |>|v asq | cdp/cdn vasq t pwocd t pwkcd transmit timing symbol parameter min. typ. max. unit conditions t predy dtpo- to tpo+ and dtpo+ to tpo- delay 47 53 ns t idl tpo+ high to idle time 250 350 ns tpo + dtpr + tpo - dtpr - t predy t idl dm9081 18 final version: dm9081-ds-f01 april 22, 1997 receive timing symbol parameter min. typ. max. unit conditions t roff rxd+ high to idle time 200 ns rxd + rxd - t roff link integrity timing symbol parameter min. typ. max. unit conditions t lp transmitted link integrity pulse period 8 16 24 ms t lpwt link integrity pulse width for tpo+ 80 100 120 ns t lpwd link integrity pulse width for dtpo+/- 40 50 60 ns tpo + dtpo + tpo - dtpo - t lpwt t lpwd t lpwd t lp dm9081 final 19 version: dm9081-ds-f01 april 22, 1997 layout recommendation decoupling the dm9081 contains both analog and digital elements. separate power pins are provided for the analog sections, the digital portion of tp line drivers, the tp line drivers, and the digital core logic. care should be taken in board design to minimize coupling of noise from the power supply and digital logic to the analog power pins. decoupling capacitors should be placed as close to the appropriate v dd and gnd pins as possible. figure 7 shows the recommended decoupling values for the dm9081 chip. figure 7. dm9081 device power s upply decouping recommendations dm9081 20 final version: dm9081-ds-f01 april 22, 1997 power plane the board power planes must be separated into analog and digital portions. the +5v and ground planes can be laid out according to the configuration shown in figure 8. the analog portion should be located under the analog power pins of the dm9081 chip and the aui logic. the digital portion should be located close enough to the 10base-t filter to attach a 0.1mf capacitor to the filter ground pin. extending the digital power plane under the 10base-t filter is not recommended. the analog and digital power planes should be co nnected at a single p oint with either a 1.8-2.2 ? or 120z ferrite bead. in the diagram below, a 47mf capacitor is used in parallel with a 0.1mf capacitor to connect the analog and digital planes. shielded rj-45 connectors are recommended. the shielded pins should be tied to the frame ground. depending on the characteristics of the 10base-t filter, either the frame ground or a void in the planes should be extended under the f ilters. con sult the filter manufacturer to determine if the frame ground is needed to minimize the effects of cross-talk within the filters. figure 8. dm9081 device power plane recommendations dm9081 final 21 version: dm9081-ds-f01 april 22, 1997 package information qfp 100l outline dimensions unit: inches/mm a 1 a 2 a seating plane 1 30 b 31 50 51 80 81 100 h d d f e h e e g e g d see detail f d y l g d ~ ~ ~ l 1 detail f c symbol dimensions in inches dimensions in mm a 0.130 max. 3.30 max. a 1 0.004 min. 0.10 min. a 2 0.112 0.005 2.85 0.13 b 0.012 +0.004 0.31 +0.10 -0.002 -0.05 c 0.006 +0.004 0.15 +0.10 -0.002 -0.05 d 0.551 0.005 14.00 0.13 e 0.787 0.005 20.00 0.13 e 0.026 0.006 0.65 0.15 f 0.742 nom. 18.85 nom. g d 0.693 nom. 17.60 nom. g e 0.929 nom. 23.60 nom. h d 0.740 0.012 18.80 0.31 h e 0.976 0.012 24.79 0.31 l 0.047 0.008 1.19 0.20 l 1 0.095 0.008 2.41 0.20 y 0.006 max. 0.15 max. 0 ~ 12 0 ~ 12 note: 1. dimensions d&e do not include resin fins. 2. dimensions g d & g e are for pc board surface mount pad pitch design reference only. 3. all dimensions are based on metric system. dm9081 final version: dm9081-ds-f01 april 22, 1997 ordering information part number pin count package DM9081F 100 qfp disclaimer ! " # " " $% &'()*(" +* , -((,. & *( ),/0. ( &,* & ( ,. 1'(1 * " 1 2 " 2 2 " 1 3 ! 3 company overview ! " # $ % # % products & % # # ' # # % # ( #) contact windows for additional information about davicom products, contact the sales department at: headquarters davicom semiconductor, inc. 1135 kern ave. sunnyvale, ca 94086 tel: 408-736-8600 fax: 408-736-8688 email: sales@davicom8.com asia operation: taipei sales office: 8f, no. 3, lane 235, bao-chiao road, hsin-tien city, taipei, taiwan, r.o.c. tel: 886-2-915-3030 fax: 886-2-915-7575 email: sales@davicom.com.tw hsin-chu office: 4f, no. 17, park avenue ii, science-based park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-8797 fax: 886-3-579-8858 customer service hot line: 080-035- 035 warning # " $ % " 4 |
Price & Availability of DM9081F
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |